In typical ASIC (Application-Specific Integrated Circuit) design process, designers firstly divide a circuit into a plurality of modules according to the needed functions of the chip circuit, and realize each module using various logic units. Those logic units can be all kinds of connectors, logic gates, registers, and so on. Generally, the connect relations among those logic units are recorded in a netlist file. According to the records in the netlist, designers can perform the primary physical placement for each logic unit.
From the viewpoint of time sequence, the logic units recorded in the netlist include combinational logic units and sequential logic units. For combinational logic units, such as all kinds of logic gates, the operating status only depends on the present inputs, not related with the history status and sequence, while sequential logic units, such as registers and latches, need clock sequence to maintain and record their previous status. Accordingly, sequential logic units have clock pins to receive clock input. In order to provide each sequential logic unit with needed clock input, a clock tree is designed for sequential logic units to show the path from the original clock source to the target sequential logic units. Generally, a clock tree consists of PLLs (Phase-Locked Loops) as clock frequency doublers and buffers for driving sequential logic units.
Then, the designed clock tree is inserted into the circuit design, and the physical placement is further adjusted accordingly. And then, clock adjustment is performed on the circuit. Finally, on the basis of timing clean, physical layout is performed, and the circuit design is finished.
In the above process of designing and inserting the clock tree, clock skew is the key point to consider. As above described, all sequential logic units of the circuit need clock signal; however the time of the clock signal arriving at different sequential logic units is different because the path from the clock source to each sequential logic unit is different. Such time difference is also called a clock skew. There are various factors leading to the clock skew, including the path length difference among different units, the load number and size difference, the difference caused by OCV (on-chip variation), etc. OCV includes manufacturing technical variation, operational voltage variation, ambient temperature variation, etc.
Ideally, in the process of designing the clock tree, the clock skew should be estimated considering all factors related to the clock, in order to obtain the clock tree with the least skew. When the clock tree is inserted, the placement can be adjusted using placement assistant tool (e.g. PDS) based on the estimated clock skew, so as to further decrease the clock skew, and finally make the sequential timing clean. Therefore, it is very important to estimate the clock skew accurately.
In the existing techniques, the clock skew is generally estimated by the designers according to the number and the position of the sequential logic units in the logic tree, or estimated using clock estimation tools. Estimation tools estimate the clock skew mainly according to factors such as buffer type, buffer fan out, chip size, etc. However, the above estimation methods are still insufficient. First, the estimation result is not accurate enough because of failing to considering all factors. Besides, the above methods usually provide a global skew value as the clock skew of a clock tree, wherein the global skew is generally the signal arriving time difference between two units which have the largest clock path difference. Obviously, such global skew cannot accurately represent the clock difference between any two units. Because of the above reasons, the clock skew estimation for each sequential logic unit in the circuit is usually not accurate, resulting in over-estimation or under-estimation. The under-estimation of clock skew will leave large sequence defect to correct after inserting the clock tree; while the over-estimation of clock skew will make placement assistant tools do excessive optimization work in order to decrease clock skew, which increases unnecessary consumption. Therefore, an optimized approach is expected to estimate the clock skew more accurately, and further improve the efficiency of ASIC design.